The present invention relates to copper (Cu) and/or Cu alloy metallization in semiconductor devices, particularly to a method for forming reliably capped Cu or Cu alloy interconnects, such as single and dual damascene structures formed in low dielectric constant materials. The present invention is particularly applicable to manufacturing high speed integrated circuits having submicron design features and high conductivity interconnects with improved electromigration resistance.
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low Rxc3x97C (resistance x capacitance) interconnect pattern with electromigration resistance, particularly wherein submicron vias, contacts and trenches have high aspect ratios imposed by miniaturization.
Conventional semiconductor devices comprise a semiconductor substrate, typically doped monocrystalline silicon, and a plurality of sequentially formed interlayer dielectrics and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor xe2x80x9cchipsxe2x80x9d comprising five or more levels of metallization are becoming more prevalent as device geometry""s shrink to submicron levels.
A conductive plug filling a via hole is typically formed by depositing an interlayer dielectric on a conductive layer comprising at least one conductive pattern, forming an opening through the interlayer dielectric by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the interlayer dielectric is typically removed by chemical mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the interlayer dielectric and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via hole section in communication with an upper trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
High performance microprocessor applications require rapid speed of semiconductor circuitry. The control speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Miniaturization demands long interconnects having small contacts and small cross-sections. As the length of metal interconnects increases and cross-sectional areas and distances between interconnects decrease, the Rxc3x97C delay caused by the interconnect wiring increases. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As design rules are reduced to about 0.12 micron and below, the rejection rate due to integrated circuit speed delays significantly reduces production throughput and increases manufacturing costs. Moreover, as line widths decrease electrical conductivity and electromigration resistance become increasingly important.
Cu and Cu alloys have received considerable attention as a candidate for replacing Al in interconnect metallizations. Cu is relatively inexpensive, easy to process, and has a lower resistively than Al. In addition, Cu has improved electrical properties vis-à-vis W, making Cu a desirable metal for use as a conductive plug as well as conductive wiring.
An approach to forming Cu plugs and wiring comprises the use of damascene structures employing CMP. However, due to Cu diffusion through interdielectric layer materials, such as silicon dioxide, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier metals include tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium (Ti), titanium-tungsten (TiW), tungsten (W), tungsten nitride (WN), Tixe2x80x94TiN, titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN) and silicon nitride for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the dielectric interlayer, but includes interfaces with other metals as well.
There are additional problems attendant upon conventional Cu interconnect methodology employing a diffusion barrier layer (capping layer). For example, conventional practices comprise forming a damascene opening in an interlayer dielectric, depositing a barrier layer such as TaN, lining the opening and on the surface of the interlayer dielectric, filling the opening with Cu or a Cu alloy layer, CMP, and forming a capping layer on the exposed surface of the Cu or Cu alloy. It was found, however, that capping layers, such as silicon nitride, deposited by plasma enhanced chemical vapor deposition (PECVD), exhibit poor adhesion to the Cu or Cu alloy surface. Consequently, the capping layer is vulnerable to removal, as by peeling due to scratching or stresses resulting from subsequent deposition of layers. As a result, the Cu or Cu alloy is not entirely encapsulated and Cu diffusion occurs, thereby adversely affecting device performance and decreasing the electromigration resistance of the Cu or Cu alloy interconnect member.
In copending application Ser. No. 09/497,850 filed on Feb. 4, 2000, a method is disclosed comprising treating the surface of a Cu or Cu alloy layer with a plasma containing nitrogen (N2) and ammonia (NH3), followed by depositing the capping layer in the presence of N2 in the same reaction chamber for improved adhesion of the capping layer to the Cu or Cu alloy interconnect. This technique has been effective in improving adhesion of the capping layer. However, after further experimentation and investigation, it was found that capped Cu or Cu alloy interconnects, as in damascene and dual damascene structures, exhibited poor electromigration resistance, particular in those cases wherein the exposed surface of the Cu or Cu alloy was treated with a plasma to remove a copper oxide surface film prior to deposition of the capping layer, e.g., silicon nitride. Such poor electromigration resistance adversely impacts device reliability and results in poor product yield.
In copending application Ser. No. 09/846,186 filed on May 2, 2001 a method of plasma treating an upper surface of inlaid Cu or Cu alloy metallization is disclosed using a relatively soft NH3 plasma treatment heavily diluted with N2, ramping up the introduction of silane (SiH4) and then initiating plasma enhanced chemical vapor deposition (PECVD) while maintaining the same pressure during plasma treatment, SiH4 ramp up and silicon nitride capping layer deposition, with an attendant significant improvement in electromigration resistance, within wafer uniformity and wafer-to-wafer uniformity.
As design rules extend deeper into the submicron range, the reliability of interconnect patterns becomes particularly critical. Therefore, the adhesion of capping layers to Cu interconnects and the accuracy of interconnects for vertical metallization levels require even greater reliability. In addition, as the design rules plunge deeper into the sub-micron regime, electromigration becomes increasingly problematic.
For example, in 0.13 micron Cu technology, vias typically exhibit a cross-sectional diameter about 0.15 to about 0.18 micron. Typical Cu damascene technology is schematically illustrated in FIG. 6 and comprises a lower Cu level, illustrated by lower metal line M1, a silicon nitride capping layer thereon, an upper metal line M2 with a silicon nitride capping layer thereon. M1 and M2 are connected by via V1. The via process typically involves a via etch through an oxide layer and a nitride layer, stopping on the underlying Cu M1. An argon (Ar) pre-sputter etch is employed prior to barrier layer and Cu deposition.
Upon further experimentation and investigation of electromigration failures attendant upon interconnect technology in the sub-micron regime, it was found that the two critical interfaces for electromigration in Cu or Cu alloy damascene are the V1-M1 and V1-M2 interfaces. Electromigration testing of the V1-M1 interface was conducted by flowing electrons from M2 through V1 into M1 lines. Electromigration testing of the V1-M2 interface was conducted by flowing electrons in the opposite direction. In the case of the V1-M1 interface, electromigration voids are typically generated at the Cu/nitride interface at the via, as shown in FIG. 7. In the case of the V1-M2 interface, electromigration voids are also generated at the Cu-nitride interface but away from the via, as schematically illustrated in FIG. 8.
Observations from such experimentation led to the conclusion that the electromigration voids are generated at the Cu-nitride interface in both cases. Diffusion can proceed along the Cu-nitride interface, the Cu-barrier layer interface or by a grain boundary mechanism. In the Cu damascene technology illustrated in FIGS. 6-8, the observations indicated that the diffusion along the Cu-nitride interface is the fastest diffusion path for electromigration failures.
Accordingly, there exists a continuing need for methodology enabling the formation of encapsulated Cu and Cu alloy interconnects for vertical metallization levels with greater accuracy, reliability and electromigration resistance. There exists a particular continuing need for methodology enabling the formation of capped Cu or Cu alloy lines, particularly in damascene structures, e.g., dual damascene structures formed in dielectric material having a low dielectric constant (k), with improved reliability and electromigration resistance along the Cu/capping layer interfaces.
An advantage of the present invention is a method of manufacturing a semiconductor device having highly reliable capped Cu or Cu alloy interconnects.
Another advantage of the present invention is a method of manufacturing a semiconductor device comprising a silicon nitride capped Cu or Cu alloy interconnect member with improved electromigration resistance along the Cu or Cu alloy/silicon nitride capping layer interface..
Additional advantages and other features of the present invention will be set forth in the description which follows and, in part, will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: introducing a wafer containing inlaid copper (Cu) or a Cu alloy into a chamber; treating an exposed surface of the Cu or Cu alloy to remove oxide therefrom; depositing a silicon nitride capping layer on the treated Cu or Cu alloy surface by plasma enhanced chemical vapor deposition (PECVD); and controlling conditions during PECVD such that the deposited silicon nitride capping layer has a compressive stress no greater than about 2xc3x97107 Pascals.
Embodiments of the present invention comprise controlling PECVD deposition conditions, such as the RF power at about 400 to about 500 watts and the spacing, between the wafer surface and the shower head through which the gases are ejected, at about 680 to about 720 mils achieving a deposition rate no greater than about 34 xc3x85/sec.
Embodiments of the present invention further include a method of manufacturing a semiconductor device, the method comprising: the sequential steps: (a) introducing a wafer containing inlaid copper (Cu) or a Cu alloy into a chamber; (b) treating an exposed surface of the Cu or Cu alloy with a plasma containing ammonia (NH3) and nitrogen (N2) in the chamber at a pressure; (c) introducing silane (SiH4) into the chamber; and (d) depositing a silicon nitride capping layer on the surface of the Cu or Cu alloy layer in the chamber at an RF power of about 400 to about 500 watts and a spacing of about 680 to about 720 mils, the method comprising conducting steps (c) and (d) while substantially maintaining the pressure used in step (b).
Embodiments of the present invention include plasma treating the exposed surface of inlaid Cu or a Cu alloy with a soft plasma comprising NH3 heavily diluted with N2, and maintaining the pressure, N2 flow rate and NH3 flow rate throughout steps (c) and (d). Embodiments of the present invention further include conducting step (c) in two stages. During the first stage (c1), SiH4 is introduced until a flow rate of about 70 to about 90 sccm is achieved, typically in about 2 to about 5 seconds, followed by stage (c2) during which the SiH4 flow rate is increased to about 130 to about 170 sccm typically over a period of about 3 seconds to about 8 seconds. Subsequently, a suitable RF power is applied, as about 400 to about 500 watts, to implement PECVD of the silicon nitride capping layer, as at a thickness of about 450 xc3x85 to about 550 xc3x85.
Embodiments of the present invention further include single and dual damascene techniques comprising forming an opening in an interlayer dielectric on a wafer, depositing an underlying diffusion barrier layer, such as Ta and/or TaN, lining the opening and on the interdielectric layer, depositing a seedlayer, depositing the Cu or a Cu alloy layer on the diffusion barrier layer filling the opening and over the interlayer dielectric, removing any portion of the Cu or Cu alloy layer beyond the opening by CMP, leaving an exposed surface oxidized, and conveying the wafer into the deposition chamber for processing in accordance with embodiments of the present invention by treating the exposed surface of the Cu or Cu alloy layer with a soft plasma employing a relatively low NH3 flow rate and a relatively high N2 flow rate, ramping up the introduction of SiH4 and then depositing a silicon nitride capping layer on the treated surface.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein embodiments of the present invention are described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.